This page presents simple large signal models of CMOS transistors and transmission gates [1].

## NMOS

The nmos transistor is modeled as shown in the equivalent circuit of the figure above. The VCCS $$i_N$$ is modeled as a linear or nonlinear function of the applied drain-source voltage $$v_{DS}$$.

### NMOS Linear Model

$$i_N(v_N) = \left\{ \begin{array}{l l} \frac{v_{DS}}{R_n} & v_{GS} \geq 0.5 \\ 0 & v_{GS} \lt 0.5 \\ \end{array} \right.$$

Charge storage effects are modeled by two linear capacitances:

$$C_{IN} = \frac{3}{2}C_{oxn}\\$$ $$C_{OUT} = C_{oxn}\\$$

where $$C_{oxn}$$ and $$R_n$$ are constants whose values are:

$$C_{oxn} = C'_{ox}WL(scale)^2 \\ \label{eq:mos_coxn}$$ $$R_n = \frac{34\times10^{3}}{W}\\ \label{eq:mos_rn}$$

The table below lists the nmos transistor model parameters.

Parameter Description Units
$$C'_{ox}$$ Oxide Capacitance per area $$F/\mu m^2$$
W Channel width
L Channel length

## PMOS

The pmos transistor is modeled as shown in the equivalent circuit of the figure above. The VCCS $$i_P$$ is modeled as a linear or nonlinear function of the applied drain-source voltage $$v_{SD}$$.

### PMOS Linear Model

$$i_N(v_N) = \left\{ \begin{array}{l l} \frac{v_{SD}}{R_p} & v_{SG} \geq -0.5 \\ 0 & v_{SG} \lt -0.5 \\ \end{array} \right.$$

Charge storage effects are modeled by two linear capacitances:

$$C_{IN} = \frac{3}{2}C_{oxp}\\$$ $$C_{OUT} = C_{oxp}\\$$

where $$C_{oxp}$$ and $$R_p$$ are constants whose values are:

$$C_{oxp} = C'_{ox}WL(scale)^2 \\ \label{eq:mos_coxp}$$ $$R_p = \frac{68\times10^{3}}{W}\\ \label{eq:mos_rp}$$

The table below lists the pmos transistor model parameters.

Parameter Description Units
$$C'_{ox}$$ Oxide Capacitance per area $$F/\mu m^2$$
W Channel width
L Channel length

## Transmission Gates

The CMOS transmission gate is modeled as shown in the equivalent circuit of the figure above. The VCCS $$i_{TG}$$ is modeled as a linear or nonlinear function of the applied drain-source voltage $$V_{TG}$$.

### Linear Model

$$i_{TG}(v_{TG}) = \left\{ \begin{array}{l l} \frac{v_{TG}}{R_{TG}} & v_{clk} \geq 0.5 \text{ and } v_{clkbar} \lt 0.5 \\ 0 & v_{clk} \lt 0.5 \text{ and } v_{clkbar} \geq 0.5 \\ \end{array} \right.$$

Where $$R_{TG}$$ may be written as:

$$R_{TG} = \frac{R_n + R_p}{R_n \times R_p} \\$$

Charge storage effects are modeled by a linear capacitance:

$$C_{TG} = C_{oxn} + C_{oxp} \\$$

Where $$C_{oxn}$$, $$C_{oxp}$$, $$R_n$$ and $$R_p$$ are given by equations \eqref{eq:mos_coxn}, \eqref{eq:mos_coxp}, \eqref{eq:mos_rn} and \eqref{eq:mos_rp} respectively.

## Octave Code

	  function f = nmos_digital(Vgs, Vds, L, W, scale, Cox_dash)

Rn = 34e3 / W;
Cox = Cox_dash * (scale^2 / (1e-6)^2) * W * L;

CIN = (3/2) * Cox;
COUT = Cox;

if(Vgs > 0.5)
ids = Vds / Rn;
else
ids = 0;
end

f=[CIN;COUT;ids];

end

function f = pmos_digital(Vsg, Vsd, L, W, scale, Cox_dash)

Rp = 68e3 / W;
Cox = Cox_dash * (scale^2 / (1e-6)^2) * W * L;

CIN = (3/2) * Cox;
COUT = Cox;

if(Vsg < -0.5)
isd = (Vsd / Rp);
else
isd = 0;
end

f=[CIN;COUT;isd];

end

function f = tg(Vtg, Vclock, Vclock_bar, Ln, Wn, Lp, Wp, scale, Cox_dash)

Rn = 34e3 / Wn;
Rp = 68e3 / Wp;

Rt = (Rn + Rp) / (Rn*Rp);

Coxn = Cox_dash * (scale^2 / (1e-6)^2) * Wn * Ln;
Coxp = Cox_dash * (scale^2 / (1e-6)^2) * Wp * Lp;

COUT = Coxn + Coxp;

if(Vclock > 0.5 & Vclock_bar < 0.5)
itg = Vtg / Rt;
else
itg = 0;
end

f=[COUT;itg];

end



## References

1. R.Jacob Baker (2008). CMOS Circuit Design, Layout and Simulation. Revised 2nd ed. New Jersey: John Wiley & Sons, Inc. Chapter 10.